1. Field of the Invention
This invention relates to the removal of heat generated by an integrated circuit and the components used in chip assembly and packaging to facilitate said heat removal. More specifically, this invention discloses the application of self-assembled nano-structures for improving the performance of heat sink structures coupled to integrated circuit devices.
2. Description of the Related Art
Prior art used to cool semiconductor ICs incorporates the use of large and expensive chip packaging having externally mounted, finned heat sinks coupled to the ceramic or plastic encapsulated IC chip. As the speed and density of modem integrated circuits increase, the power generated by these chips also increases, often in geometric proportion to increasing density and functionality. In the video processing and CPU application areas, the ability to dissipate the heat being generated by current ICs is becoming a serious limitation in the advance of technology. In the current art, relatively large interface-thermal-resistances are added when the die is ‘attached’ to a heat spreader, heat pipe or heat sink. These multiple interfaces have the undesired side effect of increasing total die to heat sink resistance and making heat transfer more difficult.
FIG. 1 (Prior Art) is a cross section schematic view of a simplified integrated circuit structure. Transistor structure 102 is formed near the top surface of substrate 100. Electrical interconnects 106 are used to make contact with transistor 102 and numerous other similar devices (not shown) on the substrate 100. “Solder balls” 104 are utilized to complete the interconnect of the integrated circuit to a printed circuit board or wire leadframe. This type of package is often referred to as a “flip chip” device. In the current art, heat generated by transistor 102 is extracted through the substrate 100 to the back surface of the chip. A heat transfer bonding layer 108 may be utilized to enhance heat conduction by reducing interfacial heat transfer resistance created by air gaps and surface irregularities. Typically, this layer may be composed of a thermal grease or thermally conductive epoxy. These materials, while better that solid surface/surface contact, still have a relatively poor thermal conductivity when compared to solid metals. As a result, the backside chip surface interface still presents a significant thermal resistance which limits the power that can be extracted from the chip.
Recently, U.S. Patent Application Publication number US2003/0117770 has disclosed a process of forming a thermal interface that employs carbon nano-tubes to reduce thermal resistance between an electronic device and a heat sink. Bundles of aligned nano-tubes receive injected polymeric material in molten form to produce a composite which is placed between the electronic device and the heat sink. The nano-tubes are aligned parallel to the direction of heat energy. However, the polymeric filler does little to spread heat laterally, potentially creating localized hot spots on the device surface. The use of bundles of aligned carbon nano-tubes may result in reduced thermal conduction as well. Theoretical molecular dynamics simulations have shown that isolated carbon nano-tubes show unusually high thermal conductivity, but that the thermal conductivity degrades by an order of magnitude when carbon nano-tube bundles are formed with tube-to-tube contacts (see for example Savas Berber, et al, Physics Review Letters, 84, no. 20, 4613, May 2000). U.S. Patent Application Publication US2003/231471 discloses an integrated circuit package that utilizes single wall or double wall carbon nano-tube arrays grown subsequent to the deposition of CVD diamond films. Due to the roughness of CVD diamond films, carbon nano-tubes are utilized to aid in making thermal contact between the surfaces of the circuit silicon die and of the integrated heat spreader. The interstitial voids between the nano-tubes are not filled in order to maintain flexibility. This disclosure, however, fails to provide any method to reduce matting and nano-tube to nano-tube contact, which reduces the effective thermal conductivity of the structure. Although CVD diamond films are good conductors, they may not be thermally compatible (from an expansion perspective) with a number of other metallic materials utilized in various heat sink structures. Additionally, commonly known techniques for growing carbon nano-tubes would preclude carbon nanotube deposition directly on a silicon circuit die, since these techniques require temperatures in the range of 700 to 800° C. Exposing a completed circuit die to these elevated temperatures is not a recommended practice.
What is needed is a method and structure by which interface resistances are minimized by integrating several thermal components to maximize heat transfer from hot surfaces on the integrated circuit.